HD6432142 datasheet(642/1177 Pages) RENESAS

642 / 1177 page

Section 18 Host Interface

Rev. 4.00 Sep 27, 2006 page 598 of 1130

REJ09B0327-0400

this pin by sending commands and data. This function is available only when register IDR1 is

accessed using

CS1. Slave logic decodes the commands input from the host processor. When an

H'D1 host command is detected, bit 1 of the data following the host command is output from the

GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the

regular processing using interrupts. Table 18.6 lists the conditions that set and clear GA20 (P81).

Figure 18.2 shows the GA20 output in flowchart form. Table 18.7 indicates the GA20 output

signal values.

Table 18.6

GA20 (P81) Set/Clear Timing

Pin Name

Setting Condition

Clearing Condition

GA20

(P81)

Rising edge of the host’s write signal

(

IOW) when bit 1 of the written data is 1

and the data follows an H'D1 host

command

Rising edge of the host’s write signal

(

IOW) when bit 1 of the written data is 0

and the data follows an H'D1 host

command

Also, when bit FGA20E in HICR is cleared

to 0

Start

Host write

H'D1 command

received?

Wait for next byte

Host write

Yes

Data byte?

Write bit 1 of data byte

to DR bit of P81/GA20

Yes

Figure 18.2 GA20 Output

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