SH7101 datasheet(98/486 Pages) RENESAS

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5. Exception Processing

Rev.2.00 Sep. 27, 2007 Page 64 of 448

REJ09B0394-0200

5.6

Cases when Exception Sources are Not Accepted

When an address error or interrupt is generated directly after a delayed branch instruction or

interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as

shown in table 5.10. In this case, it will be accepted when an instruction that can accept the

exception is decoded.

Table 5.10

Generation of Exception Sources Immediately after Delayed Branch Instruction

or Interrupt-Disabled Instruction

Exception Source

Point of Occurrence

Address Error

Interrupt

Immediately after a delayed branch instruction*

Not accepted

Immediately after an interrupt-disabled instruction*

Accepted

Not accepted

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and

BRAF

2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L

5.6.1

Immediately after Delayed Branch Instruction

When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,

neither address errors nor interrupts are accepted. The delayed branch instruction and the

instruction placed immediately after it (delay slot) are always executed consecutively, so no

exception processing occurs during this period.

5.6.2

Immediately after Interrupt-Disabled Instruction

When an instruction placed immediately after an interrupt-disabled instruction is decoded,

interrupts are not accepted. Address errors can be accepted.

SH7101 Datasheet(PDF) 98 Page - Renesas Technology Corp