SH7101 datasheet(23/486 Pages) RENESAS

23 / 486 page

Rev.2.00 Sep. 27, 2007 Page xxiii of xxxiv

REJ09B0394-0200

Figures

Section 1 Overview

Figure 1.1

Internal Block Diagram of SH7101............................................................................ 3

Figure 1.2

SH7101 Pin Arrangement .......................................................................................... 4

Section 2 CPU

Figure 2.1

CPU Internal Registers ............................................................................................. 12

Figure 2.2

Data Format in Registers .......................................................................................... 15

Figure 2.3

Data Formats in Memory ......................................................................................... 16

Figure 2.4

Transitions between Processing States ..................................................................... 41

Section 3 MCU Operating Modes

Figure 3.1

Address Map for SH7101 Mask ROM Version ....................................................... 45

Section 4 Clock Pulse Generator

Figure 4.1

Block Diagram of Clock Pulse Generator ................................................................ 47

Figure 4.2

Connection of Crystal Resonator (Example)............................................................ 48

Figure 4.3

Crystal Resonator Equivalent Circuit ....................................................................... 48

Figure 4.4

Example of External Clock Connection ................................................................... 49

Figure 4.5

Cautions for Oscillator Circuit System Board Design.............................................. 50

Figure 4.6

Recommended External Circuitry around PLL ........................................................ 51

Section 6 Interrupt Controller (INTC)

Figure 6.1

INTC Block Diagram ............................................................................................... 67

Figure 6.2

Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................ 76

Figure 6.3

Interrupt Sequence Flowchart .................................................................................. 82

Figure 6.4

Stack after Interrupt Exception Processing .............................................................. 83

Figure 6.5

Example of the Pipeline Operation when an IRQ Interrupt is Accepted.................. 85

Section 8 Multi-Function Timer Pulse Unit (MTU)

Figure 8.1

Block Diagram of MTU ........................................................................................... 94

Figure 8.2

Complementary PWM Mode Output Level Example ............................................ 132

Figure 8.3

Example of Counter Operation Setting Procedure ................................................. 137

Figure 8.4

Free-Running Counter Operation ........................................................................... 138

Figure 8.5

Periodic Counter Operation.................................................................................... 139

Figure 8.6

Example of Setting Procedure for Waveform Output by Compare Match............. 139

Figure 8.7

Example of 0 Output/1 Output Operation .............................................................. 140

Figure 8.8

Example of Toggle Output Operation .................................................................... 140

Figure 8.9

Example of Input Capture Operation Setting Procedure ........................................ 141

Figure 8.10

Example of Input Capture Operation ..................................................................... 142

Figure 8.11

Example of Synchronous Operation Setting Procedure ......................................... 143

Figure 8.12

Example of Synchronous Operation....................................................................... 144

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