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SH7101 Datasheet(PDF) 31 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  486 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 31 Page - Renesas Technology Corp

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Rev.2.00 Sep. 27, 2007 Page xxxi of xxxiv
REJ09B0394-0200
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................... 5
Table 1.2
Differences from SH7046 Group ................................................................................. 9
Section 2 CPU
Table 2.1
Initial Values of Registers.......................................................................................... 15
Table 2.2
Sign Extension of Word Data .................................................................................... 17
Table 2.3
Delayed Branch Instructions...................................................................................... 17
Table 2.4
T Bit ...........................................................................................................................18
Table 2.5
Immediate Data Accessing......................................................................................... 18
Table 2.6
Absolute Address Accessing...................................................................................... 19
Table 2.7
Displacement Accessing ............................................................................................ 19
Table 2.8
Addressing Modes and Effective Addresses.............................................................. 20
Table 2.9
Instruction Formats .................................................................................................... 24
Table 2.10
Classification of Instructions ..................................................................................... 27
Table 2.11
Symbols Used in Instruction Code, Operation, and Execution States Tables ............ 30
Table 2.12
Data Transfer Instructions.......................................................................................... 31
Table 2.13
Arithmetic Operation Instructions ............................................................................. 33
Table 2.14
Logic Operation Instructions ..................................................................................... 36
Table 2.15
Shift Instructions........................................................................................................ 37
Table 2.16
Branch Instructions .................................................................................................... 38
Table 2.17
System Control Instructions....................................................................................... 39
Section 3 MCU Operating Modes
Table 3.1
Selection of Operating Modes.................................................................................... 43
Table 3.2
Maximum Operating Clock Frequency for Each Clock Mode .................................. 43
Table 3.3
Operating Mode Pin Configuration............................................................................ 44
Section 4 Clock Pulse Generator
Table 4.1
Damping Resistance Values....................................................................................... 48
Table 4.2
Crystal Resonator Characteristics .............................................................................. 48
Section 5 Exception Processing
Table 5.1
Types of Exception Processing and Priority .............................................................. 53
Table 5.2
Timing for Exception Source Detection and Start of Exception Processing.............. 54
Table 5.3
Exception Processing Vector Table ........................................................................... 55
Table 5.4
Calculating Exception Processing Vector Table Addresses....................................... 56
Table 5.5
Reset Status................................................................................................................ 57
Table 5.6
Bus Cycles and Address Errors.................................................................................. 59
Table 5.7
Interrupt Sources........................................................................................................ 60



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