SH7101 datasheet(10/486 Pages) RENESAS

10 / 486 page

Rev.2.00 Sep. 27, 2007 Page x of xxxiv

REJ09B0394-0200

Item

Page

Revision (See Manual for Details)

8.9.5 Usage Note

262

Description added

(1) Symptom

(a) Regarding the POEnF*1 bits

If setting of the POEnF bits in the input level control/status

registers (ICSR1 and ICSR2) by the hardware*2 and reading

from these bits occur simultaneously, “0” will be read, where “1”

should be read.

Furthermore, if clearing of these bits is attempted subsequent

to the above condition, the clearing should be ignored*3 but it

will be carried out.

Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to

6; for the SH7144-Series, n = 0 to 3.

*2 The POEnF bits are set when the signals input to the

respective POEn pins satisfy the conditions that are

specified by the POEnM1 and POEnM0 of the

ICSR1 and ICSR2.

*3 The correct operation is that clearing of the POEnF

bits is only possible after “1” is read from them in

order to prevent accidental clearing.

(b) Regarding the OSF bit

The same symptom applies to the OSF bits of the output level

control/status register (OCSR).

(2) To Avoid This Problem

Please clear the POEnF bits or the OSF bit in these steps: first

execute a read for ICSR1, ICSR2, or OCSR, then write “0” to

the bits that had a read value of “1” to clear them while writing

“1” to other bits. If this procedure is not followed, the POEnF

bits and the OSF bit may be cleared unexpectedly if their

setting by hardware and reading occur simultaneously.

10.3.2 Receive Data

280

Description added

... RDR cannot be written to by the CPU. The initial value of

RDR is H'00.

10.3.4 Transmit Data

280

Description added

... Although TDR can be read or written to by the CPU at all

times, to achieve reliable serial transmission, write transmit

data to TDR for only once after confirming that the TDRE bit in

SSR is set to 1. The initial value of TDR is H'FF.

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