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SH7101 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 560 page ![]() Section 1 Overview Rev.1.00 Sep. 18, 2008 Page 1 of 522 REJ09B0069-0100 Section 1 Overview The SH7108 Series single-chip RISC microprocessor integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The SH7108 Series CPU has a RISC-type instruction set . Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed . In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. In addition, the SH7108 Series includes on-chip peripheral functions necessary for system configuration, such as ROM, RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. As the on-chip ROM, only masked ROM version is available. However, when F-ZTAT (Flexible Zero Turn Around Time) version is required, the SH7046F (80 pins) or SH7047F (100 pins) can be used. 1.1 Features • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture ⎯ Instruction length: 16-bit fixed length for improved code efficiency ⎯ Load-store architecture (basic operations are executed between registers) ⎯ Sixteen 32-bit general registers ⎯ Five-stage pipeline ⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles ⎯ C language-oriented 62 basic instructions • Various peripheral functions ⎯ Multifunction timer/pulse unit (MTU) ⎯ Motor management timer(MMT) ⎯ Compare match timer (CMT) ⎯ Watchdog timer (WDT) ⎯ Asynchronous or clocked synchronous serial communication interface (SCI) ⎯ 10-bit A/D converter ⎯ Clock pulse generator |
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