SH7101 datasheet(18/560 Pages) RENESAS

18 / 560 page

Rev.1.00 Sep. 18, 2008 Page xviii of xxxiv

REJ09B0069-0100

15.3.2 Port D Data Register L (PDDRL) ........................................................................ 435

15.4

Port E ................................................................................................................................ 436

15.4.1 Register Descriptions ........................................................................................... 437

15.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 438

15.5

Port F................................................................................................................................. 440

15.5.1 Register Description............................................................................................. 441

15.5.2 Port F Data Register (PFDR) ............................................................................... 441

15.6

Port G................................................................................................................................ 442

15.6.1 Register Description............................................................................................. 442

15.6.2 Port G Data Register (PGDR).............................................................................. 442

Section 16 Masked ROM ..................................................................................445

16.1

Usage Note........................................................................................................................ 446

Section 17 RAM ................................................................................................447

17.1

Usage Note........................................................................................................................ 447

Section 18 Power-Down Modes ........................................................................449

18.1

Input/Output Pins .............................................................................................................. 452

18.2

Register Descriptions ........................................................................................................ 452

18.2.1 Standby Control Register (SBYCR) .................................................................... 453

18.2.2 System Control Register (SYSCR) ...................................................................... 454

18.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2) ............... 454

18.3

Operation .......................................................................................................................... 456

18.3.1 Sleep Mode .......................................................................................................... 456

18.3.2 Software Standby Mode....................................................................................... 457

18.3.3 Hardware Standby Mode ..................................................................................... 460

18.3.4 Module Standby Mode......................................................................................... 461

18.4

Usage Notes ...................................................................................................................... 462

18.4.1 I/O Port Status...................................................................................................... 462

18.4.2 Current Consumption during Oscillation Stabilization Wait Period.................... 462

18.4.3 On-Chip Peripheral Module Interrupt.................................................................. 462

18.4.4 Writing to MSTCR1 and MSTCR2 ..................................................................... 462

Section 19 List of Registers...............................................................................463

19.1

19.2

Register Bits...................................................................................................................... 471

19.3

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