SH7101 datasheet(10/560 Pages) RENESAS

10 / 560 page

Rev.1.00 Sep. 18, 2008 Page x of xxxiv

REJ09B0069-0100

3.5

Initial State of This LSI.....................................................................................................

Section 4 Clock Pulse Generator ....................................................................... 55

4.1

Oscillator...........................................................................................................................

4.1.1

Connecting a Crystal Resonator...........................................................................

4.1.2

External Clock Input Method...............................................................................

4.2

Function for Detecting the Oscillator Halt ........................................................................

4.3

Usage Notes ......................................................................................................................

4.3.1

Note on Crystal Resonator ...................................................................................

4.3.2

Notes on Board Design ........................................................................................

Section 5 Exception Processing......................................................................... 59

5.1

Overview...........................................................................................................................

5.1.1

Types of Exception Processing and Priority ........................................................

5.1.2

Exception Processing Operations.........................................................................

5.1.3

Exception Processing Vector Table .....................................................................

5.2

Resets ................................................................................................................................

5.2.1

Types of Reset .....................................................................................................

5.2.2

Power-On Reset ...................................................................................................

5.2.3

Manual Reset .......................................................................................................

5.3

Address Errors ..................................................................................................................

5.3.1

The Cause of Address Error Exception................................................................

5.3.2

Address Error Exception Processing....................................................................

5.4

Interrupts ...........................................................................................................................

5.4.1

Interrupt Sources..................................................................................................

5.4.2

Interrupt Priority Level ........................................................................................

5.4.3

Interrupt Exception Processing ............................................................................

5.5

Exceptions Triggered by Instructions ...............................................................................

5.5.1

Types of Exceptions Triggered by Instructions ...................................................

5.5.2

Trap Instructions ..................................................................................................

5.5.3

Illegal Slot Instructions ........................................................................................

5.5.4

General Illegal Instructions..................................................................................

5.6

Cases when Exception Sources Are Not Accepted ...........................................................

5.6.1

Immediately after a Delayed Branch Instruction .................................................

5.6.2

Immediately after an Interrupt-Disabled Instruction............................................

5.7

Stack Status after Exception Processing Ends ..................................................................

5.8

Usage Notes ......................................................................................................................

5.8.1

Value of Stack Pointer (SP) .................................................................................

5.8.2

Value of Vector Base Register (VBR) .................................................................

5.8.3

Address Errors Caused by Stacking of Address Error Exception Processing......

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