R5F2135CANFP datasheet(84/766 Pages) RENESAS

84 / 766 page

R8C/35A Group

6. Voltage Detection Circuit

REJ09B0407-0010 Rev.0.10

Jan 16, 2008

Page 53 of 728

Under development Preliminary specification

Specifications in this manual are tentative and subject to change

Figure 6.6

Operating Example of Voltage Monitor 1 Interrupt

Vdet1

VW1C3 bit

VCC

The above applies when:

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled)

Note:

1. If voltage monitor 0 reset is not used, set the power supply to VCC

≥ 1.8 V.

1.8 V (1)

Sampling clock of

digital filter

× 2 cycles

VW1C2 bit

VW1C1 bit is set to 1

(digital filter disabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 0

(when VCC reaches Vdet1

or above)

VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register

VCAC1: Bit in VCAC register

Sampling clock of

digital filter

× 2 cycles

Set to 0 by a program.

Voltage monitor 1

interrupt request

Voltage monitor 1

interrupt request

Set to 0 when an interrupt request

is acknowledged.

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled)

and

VCAC1 bit is set to 1

(both edges)

VW1C2 bit

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 0

(when VCC reaches Vdet1

or above)

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 1

(when VCC reaches Vdet1

or below)

Set to 0 by a program.

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 1

(digital filter disabled)

and

VCAC1 bit is set to 1

(both edges)

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

VW1C1 bit is set to 1

(digital filter disabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 1

(when VCC reaches Vdet1

or below)

Set to 0 when an interrupt request

is acknowledged.

Set to 0 when an interrupt request

is acknowledged.

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