SH7708 datasheet(230/633 Pages) RENESAS

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Bit 5—Memory Data Size (SZ): Specifies the memory data bus size for DRAM, synchronous

DRAM, and pseudo-SRAM. Always set this bit to 1 when synchronous DRAM is used. Takes

precedence over the BCR2 register designation.

Bit 5: SZ

Description

Word (16-bit)

(Initial value)

Longword (32-bit)

Bits 4 and 3—Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for

DRAM and synchronous DRAM. The actual address shift value differs between DRAM interface

and synchronous DRAM interface.

For DRAM Interface:

Bit 4: AMX1

Bit 3: AMX0

Description

8-bit column address product

(Initial value)

9-bit column address product

10-bit column address product

11-bit column address product

For Synchronous DRAM Interface:

Bit 4: AMX1

Bit 3: AMX0

Description

16-Mbit product (1M

× 16 bits)

(Initial value)

16-Mbit product (2M

× 8 bits)

16-Mbit product (4M

× 4 bits)

4-Mbit product (256k

× 16 bits)

Bit 2—Refresh Control (RFSH): Determines whether or not refreshing of DRAM, synchronous

DRAM, and pseudo-SRAM is performed. The timer for generation of the refresh request

frequency can also be used as an interval timer.

Bit 2: RFSH

Description

No refresh

(Initial value)

Refresh

SH7708 Datasheet(PDF) 230 Page - Renesas Technology Corp

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