7733 datasheet(136/940 Pages) RENESAS

136 / 940 page

TIMER A

7733 Group User’s Manual

6–25

6.4.2 Operation in event counter mode

When the count start flag is set to “1,” the counter starts counting of the count source.

The counter counts the count source’s valid edges.

When an underflow or overflow occurs, the reload register’s contents is reloaded, and then counting is

continued.

The timer Ai interrupt request bit is set to “1” when the underflow or overflow occurs in .

After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the

interrupt request bit is cleared to “0” by software.

Figure 6.4.5 shows an operation example in the event counter mode.

6.4 Event counter mode

Fig. 6.4.5 Operation example in event counter mode (without free-run count function, pulse output

function, and two-phase pulse signal processing function)

Timer Ai interrupt

request bit

FFFF16

000016

Time

Count start

flag

“1”

n = Reload register’s contents

Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software

Set to “1” by software

Counting is started.

Up-down flag “1”

g The above is applied when the up-down flag’s content is selected as the up-down switching factor (i.e., up-down

switching factor selection bit = “0”).

“0”

Set to “1” by software

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