7733 datasheet(212/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–9

CTS

enable bit

Bit

BRG count source selection

bits

Bit name

At reset

Functions

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

UART2 transmit/receive control register 0 (address 68 16)

b1 b0

0: The CTS function is enabled.

1: The CTS function is disabled. (P8 0 and P84

function as programmable I/O ports.)

Transmission register empty

flag

Not implemented.

7 to 4

0: Data is present in the transmission

1: No data is present in the transmission

Un-

defined

Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

Fig. 8.2.5 Structure of UARTi transmit/receive control register 0 (2)

(1)

____ ____

CTS

/RTS function selection bit (bit 2) (UART0, UART1)

____ ____

This bit becomes valid when the CTS/RTS enable bit (bit 6) is cleared to “0.”

____

When this bit is cleared to “0” in order to select the CTS function, the P80 and P84 pins function as

____

CTS

input pins. At this time, a “L”-level signal input to the CTS pin is one of the transmit conditions.

____

When this bit is set to “1” in order to select the RTS function, the P80 and P84 pins function as RTS

output pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (in other words,

____

reception is disabled.), the RTS pin outputs “H” level.

____

In the clock synchronous serial I/O mode, the output level of RTS pin becomes “L” when receive

conditions are satisfied; it becomes “H” when reception is started. Note that, when an internal clock

____

is selected (bit 3 at addresses 3016, 3816 = “0”), the RTS function is ignored.

____

In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes “L” when receive

enable bit is set to “1”; it becomes “H” when reception is started; it becomes “L” when the reception

is completed.

____

(2) CTS enable bit (bit 2) (UART2)

____

CTS

input pin is valid when this bit is set to “0.”

____

A “L”-level signal input to the CTS pin is one of the transmit conditions.

(3) Transmission register empty flag (bit 3)

This flag is cleared to “0” when the contents of the UARTi transmission buffer register is transferred

to the UARTi transmission register. When transmission is completed and the UARTi transmission

8.2 Block description

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