TDA9106 datasheet(19/30 Pages) STMICROELECTRONICS

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II - HORIZONTAL PART

II.1 - Internal Input Conditions

Horizontal part is internally fed by synchro proces-

sor with a digital signal. corresponding to horizontal

synchro pulses or to TTL composite input.

Concerning the duty cycle of the input signal, the

following signals (positive or negative) may be

applied to the circuit.

Using internal integration, both signals are recog-

nized on condition that Z/T < 25%. Synchronization

occurs on the leading edge of the internal sync

signal. The minimum value of Z is 0.7

µs.

OPERATING DESCRIPTION (continued)

Figure 6

An other integration is able to extract vertical pulse

of composite synchroif duty cycle is more than 25%

(typically d = 35%).

TRAMEXT

Figure 7

The last feature performed is the equalizing pulses

removing to avoid parasitic pulses on phase com-

paratorinput which is intolerent to wrong or missing

pulse.

II.2 - PLL1

The PLL1 is composed of a phase comparator, an

external filter and a voltage controlled oscillator

(VCO).

The phase comparator is a “phase frequency” type

designed in CMOS technology. This kind of phase

detector avoids locking on false frequencies. It is

followed by a “charge pump”, composed of two

current sources sunk and sourced (I = 1mA Typ.

when locked, I = 140

µA when unlocked). This

difference between lock/unlock permits a smooth

catching of horizontal frequency by PLL1. This

effectis reinforcedby an internal original slow down

system when PLL1 is locked avoiding Horizontal

too fast frequency change.

The dynamic behaviour of the PLL is fixed by an

external filter which integrates the current of the

charge pump. A “CRC” filter is generally used (see

Figure 8).

PLL1 is internally inhibited during extracted vertical

sync (if any) to avoid taking in account missing

pulses or wrong pulses on phase comparator.The

inhibition results from the opening of a switch lo-

cated between the charge pump and the filter (see

Figure 9). For particular synchro type, MCU can

drive Pin 3 to high level (TTL compatible input) to

inhibit PLL1. It can also be used to avoid PLL1

locking on synchro inputs if a “dangerous” mode is

detected by the MCU.

The VCO uses an external RC network. It delivers

a linear sawtooth obtained by charge and dis-

charge of the capacitor, by a current proportionnal

to the current in the resistor. Typical thresholds of

sawtooth are 1.6V and 6.4V. These two levels are

accessible to be filtered as on Figure 10 to improve

jitter.

The control voltage of the VCO is typically com-

prised between 1.33V and 6V (see Figure 10). The

theorical frequency range of this VCO is in the ratio

1 to 4.5, the effective frequency range has to be

smaller 1 to 4.2 due to clamp intervention on filter

lowest value. To avoid spread of external compo-

nents and the circuit itself, it is possible to adjust

free running frequency through I

2C. This adjust-

ment can be made automatically on the manufac-

turing line without manual operation by using

Hlock/unlock information. The adjustment range is

0.8 to 1.3 F0 (where 1.3 F0 is the free running

frequency at power on reset).

The synchro frequency has to be always higher

than the free running frequency. As an example for

a synchro range from 24kHz to 100kHz, the sug-

gested free running frequency is 23kHz.

PLL1F

Figure 8

TDA9106

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