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TDA9106A Datasheet(PDF) 5 Page - STMicroelectronics

Part # TDA9106A
Description  LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PDF  30 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

TDA9106A Datasheet(HTML) 5 Page - STMicroelectronics

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ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Supply Voltage (Pin 18)
13.5
V
VDD
Supply Voltage (Pin 39)
5.7
V
VIN
Max Voltage on Pin 6
Pins 15, 21, 22, 23
Pin 1
Pin 4
Pins 3, 33,34,37,38,40,41
Pin 16
Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30
1.8
12
3.6
4
5
6
8
V
V
V
V
V
V
V
VESD
ESD susceptibility
Human Body Model,100pF Discharge through 1.5k
Ω
EIAJ Norm,200pF Discharge through 0
Ω
2
300
kV
V
Tstg
Storage Temperature
-40, +150
oC
Tj
Junction Temperature
+150
oC
Toper
Operating Temperature
0, +70
oC
THERMAL DATA
Symbol
Parameter
Value
Unit
Rth (j-a)
Junction-ambient Thermal Resistance
Max.
65
oC/W
SYNCHRO PROCESSOR
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
HsVR
Horizontal Sync Input Voltage
Pin 38
0
5
V
MinD
Minimum Horizontal Input Pulses Duration
Pin 38
0.7
µs
Mduty
Maximum Horizontal Input Signal Duty Cycle
Pin 38
25
%
VsVR
Vertical Sync Input Voltage
Pin 33
0
5
V
VSW
Minimum Vertical Sync Pulse Width
Pin 33
5
µs
VSmD
Maximum Vertical Sync Input Duty Cycle
Pin 33
15
%
VextM
M ax i m um V er t ic al Syn c W i dt h on T T L
H/Vcomposite or S/G
Pins 1, 38
750
µs
Electrical Characteristics (VDD =5V, Tamb =25
oC)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VSGDC
S/G Clamped DC Level
Pin 1, I1 =-1
µA1
V
ISGbias
Internal Diode Bias Current
Pin 1, V1 = 1.6V
10
µA
VSGTh
Slicing Level (see application design choice)
Pin 1
0.2
V
VINTH
H o r iz on t al a n d V ert i cal I npu t V o lt a ge
(Pins 33,38)
Low Level
High Level
2.2
0.8
V
V
RIN
Horizontal and Vertical Pull-Up Resistor
Pins 33,38
200
k
Ω
VOut
Output Voltage (Pins 35,36,37)
Low level
High Level
0
5
V
V
TfrOut
Falling and Rising Output CMOS Buffer
Pins 35,36,37
Cout = 20pF
100
ns
VHlock
Horizontal 1st PLL Lock Output Status (Pin 37)
Locked
Unlocked
0
5
V
V
VoutT
Extracted Vsync Integration Time (% of TH) on
H/V Composite or S/G
Pin 35, C0 = 820pF
26
35
%
TDA9106A
5/30



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