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AD9239 Datasheet(PDF) 5 Page - Analog Devices |
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AD9239 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 40 page  AD9239 Rev. 0 | Page 5 of 40 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. AD9239BCPZ-170 AD9239BCPZ-210 AD9239BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK–) Logic Compliance Full LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS LVPECL/LVDS/CMOS Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V Internal Common-Mode Bias Full 1.2 1.2 1.2 V Input Common-Mode Voltage Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V High Level Input Current (IIH) Full −10 +10 −10 +10 −10 +10 μA Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 μA Differential Input Resistance 25°C 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC INPUTS (PDWN, CSB, SDI/ SDIO, SCLK, RESET, PGMx)2 Logic 1 Voltage Full 0.8 × AVDD 0.8 × AVDD 0.8 × AVDD V Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD 0.2 × AVDD V Logic 1 Input Current (CSB) Full 0 0 0 μA Logic 0 Input Current (CSB) Full −60 −60 −60 μA Logic 1 Input Current (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Full 55 55 55 μA Logic 0 Input Current (SCLK, PDWN, SDI/SDIO, RESET, PGMx) Full 0 0 0 μA Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 4 4 4 pF LOGIC OUTPUTS (SDO) Logic 1 Voltage Full 1.2 AVDD + 0.3 1.2 AVDD + 0.3 1.2 AVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V DIGITAL OUTPUTS (DOUT + x, DOUT − x) Logic Compliance Current mode logic Current mode logic Current mode logic Differential Output Voltage Full 0.8 0.8 0.8 V Common-Mode Level Full DRVDD/2 DRVDD/2 DRVDD/2 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. 2 Specified for 13 SDI/SDIO pins sharing the same connection. |
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