TDF8553J datasheet(23/47 Pages) NXP

23 / 47 page

TDF8553J_1

Objective data sheet

Rev. 01 — 3 December 2008

23 of 47

NXP Semiconductors

TDF8553J

× 50 Watt power ampliﬁer and multiple voltage regulator

11. Characteristics

Table 16.

Characteristics

Tamb =25 °C; VDCDC; VP = 14.4 V; RL =4 Ω; measured in the test circuit Figure 26; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Ampliﬁer section

Supply voltage behavior

VP(oper)

operating supply voltage

RL =4 Ω

14.4

RL =2 Ω

14.4

Iq(tot)

total quiescent current

no load

280

400

Istb

standby current

µA

output voltage

7.2

VP(low)(mute)

low supply voltage mute

6.5

Vhr

headroom voltage

when headroom protection is

activated; see Figure 4

1.4

VPOR

power-on reset voltage

see Figure 13

5.5

VO(offset)

output offset voltage

mute mode and power on

−100

+100

Mode select (pin STB)

VSTB

voltage on pin STB

standby mode

1.3

operating mode

2.5

5.5

mute mode

input current

VSTB =5V

µA

Start-up, shut-down and mute timing

twake

wake-up time

from standby before ﬁrst

I2C-bus transmission is

recognized; via pin STB; see

Figure 12

300

500

µs

td(mute_off)

mute off delay time

via I2C-bus (IB1 bit D0);

CSVR =22 µF; see Figure 12

250

td(mute-on)

delay time from mute to on

soft mute; via I2C-bus

(IB2 bit D1 = 1 to 0)

hard mute; via I2C-bus

(IB2 bit D0 = 1 to 0)

via pin STB;

VSTB =8Vto4V

td(on-mute)

delay time from on to mute

soft mute; via I2C-bus

(IB2 bit D1 = 0 to 1)

hard mute; via I2C-bus

(IB2 bit D0 = 0 to 1)

0.4

via pin STB;

VSTB =4Vto8V

0.4

I2C-bus interface

VIL

LOW-level input voltage

on pins SCL and SDA

1.5

VIH

HIGH-level input voltage

on pins SCL and SDA

2.3

5.5

VOL

LOW-level output voltage

on pin SDA; Iload = 3 mA

0.4

fSCL

SCL clock frequency

400

kHz

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