CS5461A datasheet(29/44 Pages) CIRRUS

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CS5461A

DS661F2

6.10 Status Register and Mask Register ( Status , Mask )

Address: 15 (Status); 26 (Mask)

Default =

0x000001 (Status Register), 0x000000 (Mask Register)

The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit

to reset. Writing a '0' to a bit will not change it’s current state.

The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the

corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.

DRDY

Data Ready. During conversions, this bit will indicate the end of computation cycles. For cali-

brations, this bit indicates the end of a calibration sequence.

CRDY

Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.

IOR

Current Out of Range. Set when the Instantaneous Current Register overflows.

VOR

Voltage Out of Range. Set when the Instantaneous Voltage Register overflows.

IROR

IRMS Out of Range. Set when the IRMS Register overflows.

VROR

VRMS Out of Range. Set when the VRMS Register overflows.

EOR

Energy Out of Range. Set when PACTIVE overflows.

TUP

Temperature Updated. Indicates the Temperature Register has updated.

TOD

Modulator oscillation detected on the temperature channel. Set when the modulator oscillates

due to an input above full scale.

VOD (IOD)

Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil-

lates due to an input above full scale. The level at which the modulator oscillates is significantly

higher than the voltage (current) channel’s differential input voltage range.

Note:

The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the

power line. This event should not be confused with a DC overload situation at the in-

puts, when the IOD and VOD bits will re-assert themselves even after being cleared,

multiple times.

LSD

Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-

old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON

pin rises back above the high-voltage threshold (PMHI).

VSAG

Indicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19.

Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta-

tus Register has not been successfully read.

DRDY

CRDY

IOR

VOR

IROR

VROR

EOR

654

TUP

TOD

VOD

IOD

LSD

VSAG

CS5461A Datasheet(PDF) 29 Page - Cirrus Logic

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