ML5800DM datasheet(19/25 Pages) MICRO-LINEAR

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ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

DATA BIT

NAME

DESCRIPTION

USE

B15 (MSB) / DB13

Reserved

Set bit to 0

B14 / DB12

Reserved

Set bit to 0

B13 / DB11

V23PLL

Low Voltage PLL Regulator

0: PLL Regulator set to 2.7V

1: PLL Regulator set to 2.3V

B12 / DB10

NODP

No Dither

0: 2

nd order Fractional-N

1: 1

st order Fractional-N

B11 / DB9

RCLP

RSSI Clip Enable

0: RSSI hardware clipping

1: No RSSI clipping

B10 / DB8

LVLO

Low Voltage Lockout

0: PAON unaffected by low voltage events

1: PAON gated by latched low voltage lockout

B9 / DB7

TXOL

Transmit PLL Mode

0: Closed Loop in Transmit mode

1: Open Loop in Transmit mode

B8 / DB6

TXM

TX RF Output Mode

0: TXO always on in Transmit mode

1: TXO follows PAON signal

B7 / DB5

TPC

Transmit Power Control

0: AOUT pin pulled to ground

1: AOUT pin high impedance

B6 / DB4

TXCW

Transmit Test Mode

0: FSK modulation in Transmit mode

1: CW in Transmit mode (no modulation)

B5 / DB3

LOL

PLL IF Shift Configuration

0: -1.024MHz LO Shift in Receive

1: +1.024MHz LO Shift in Receive

B4 / DB2

AOUT

Analog Output

0: AOUT pin is Transmit Power Control

1: AOUT pin is Analog Data Out

B3 / DB1

RD0

Reference Frequency Select

0: 6.144MHz nominal reference frequency

1: 12.288MHz nominal reference frequency (preferred)

B2 / DB0

QPP

PLL Charge Pump Polarity

0: Fc < Fref; Charge pump sources current

1: Fc < Fref; Charge pump sinks current

B1 / ADR1

ADR1

MSB Address Bit

ADR1 = 0

B0 (LSB) / ADR0

ADR0

LSB Address Bit

ADR0 = 0

Table 4: Register 0 - PLL Configuration Register

QPP

Charge Pump Polarity:

This bit sets the charge pump polarity to sink

or source current. For a majority of applications, this bit is cleared

(QPP = 0). For applications where an external inverting amplifier is in

the loop filter, this bit is set to 1 to change the charge pump polarity

(see Table 5).

QPP

PLL CHARGE PUMP POLARITY

For Fc < Fref. Charge pump sources current.

For Fc < Fref. Charge pump sinks current.

Table 5: PLL Charge Pump Polarity

RD0

Reference Divider:

This bit sets the reference divider from the FREF

pin to the reference input of the PLL phase/frequency detector (see

Table 6

RD0

REFERENCE

DIVISION

NOMINAL REFERENCE

FREQUENCY

6.144 MHz

12.288 MHz

Table 6. Reference Frequency Select

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