AX2000-1CSG896 datasheet(79/226 Pages) ACTEL

79 / 226 page

Axcelerator Family FPGAs

v2.7

2-65

PLL Configurations

The following rules apply to the different PLL inputs and

outputs:

Reference Clock

The RefCLK can be driven by (Figure 2-50):

1. Global routed clocks (CLKE/F/G/H) or user-created

clock network

2. CLK1 output of an adjacent PLL

3. [H]CLKxP (single-ended or voltage-referenced)

4. [H]CLKxP/[H]CLKxN

pair

(differential

modes

LVPECL or LVDS)

Feedback Clock

The feedback clock can be driven by (Figure 2-51 on page

2-66):

1. Global routed clocks (CLKE/F/G/H) or user-created

clock network

2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL

cell

3. An internal signal from the PLL block

PLLSEL

Input

ROOTSEL & PLLSEL are used to select the source of the global

clock network

ROOTSEL

Input

Lock

Output

Yes

High value indicates PLL has locked

CLK1

Output

Yes

PLL clock output

CLK2

Output

Yes

PLL clock output

Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate.

Note: Not all signals are available to the user.

Figure 2-49 • PLL Logical Interface

Table 2-79 • PLL Interface Signals (Continued)

Signal Name

Type

User Accessible

Allowable Values

Function

RefCLK

CLK1

CLK2

REFSEL

ROOTSEL

FBMuxSEL

[H]CLKINT

[H]CLKxP

[H]CLKxN

I/O

Core net

CLK net

FBINT

CLKINT

CLK1 (PLLn-1)

[H]CLK

To PLLn+1

PLLSEL

OUTSEL

CLK Out

(Routed net out pin)

PLL

Figure 2-50 • Reference Clock Connections

Non-clock

Pins

INBUF

PLL

RefCLK

PLL

RefCLK

PLL

CLK1

Regular, LVPECL, or LVDS IOPAD

Any macro from the core, except HCLK nets

For cascading

Logic

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