AX2000-1CSG896 datasheet(26/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 12

v2.7

5V Tolerance

There are two schemes to achieve 5V tolerance:

1. 3.3V PCI and 3.3V PCI-X are the only I/O standards

that directly allow 5V tolerance. To implement this,

an internal clamp diode between the input pad and

the VCCI pad is enabled so that the voltage at the

input pin is clamped as shown in EQ 2-3:

Vinput = VCCI + Vdiode = 3.3V + 0.8V = 4.1V

EQ 2-3

An external series resister (~100

Ω) is required between

the input pin and the 5V signal source to limit the

current (Figure 2-3).

2. 5V tolerance can also be achieved with 3.3V I/O

standards (3.3V PCI, 3.3V PCI-X, and LVTTL) using a

bus-switch product (e.g. IDTQS32X2384). This will

convert the 5V signal to a 3.3V signal with minimum

delay (Figure 2-4).

Simultaneous Switching Outputs (SSO)

When multiple output drivers switch simultaneously,

they induce a voltage drop in the chip/package power

distribution. This simultaneous switching momentarily

raises the ground voltage within the device relative to

the system ground. This apparent shift in the ground

potential to a non-zero value is known as simultaneous

switching noise (SSN) or more commonly, ground

bounce.

SSN becomes more of an issue in high pin count

packages and when using high performance devices such

as the Axcelerator family. Based upon testing, Actel

recommends that users not exceed eight simultaneous

switching outputs (SSO) per each VCCI/GND pair. To ease

this potential burden on designers, Actel has designed all

of the Axcelerator BGAs3 to not exceed this limit with

the exception of the CS180, which has an I/O to VCCI/GND

pair ratio of nine to one.

Please refer to the Simultaneous Switching Noise and

Signal Integrity application note for more information.

I/O Banks and Compatibility

Since each I/O bank has its own user-assigned input

reference voltage (VREF) and an input/output supply

voltage (VCCI), only I/Os with compatible standards can

be assigned to the same bank.

Table 2-11 shows the compatible I/O standards for a

common

VREF

(for

voltage-referenced

standards).

Similarly, Table 2-12 shows compatible standards for a

common VCCI.

Table 2-13

on page 2-13

summarizes

the

different

combinations of voltages and I/O standards that can be

used together in the same I/O bank. Note that two I/O

standards are compatible if:

•

Their VCCI values are identical.

•

Their VREF standards are identical (if applicable).

Figure 2-3 • Use of an External Resistor for 5V Tolerance

Figure 2-4 • Bus Switch IDTQS32X2384

Non-Actel Part

Actel FPGA

3.3V

PCI

clamp

diode

Rext

3.3V

20X

3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.

Table 2-11 • Compatible I/O Standards for Different VREF

Values

VREF

Compatible Standards

1.5V

SSTL 3 (Class I and II)

1.25V

SSTL 2 (Class I and II)

1.0V

GTL+ (2.5V and 3.3V Outputs)

0.75V

HSTL (Class I)

Table 2-12 • Compatible I/O Standards for Different VCCI

Values

VCCI

Compatible Standards

VREF

3.3V

LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3V

1.0

3.3V

SSTL 3 (Class I and II), LVTTL, PCI, LVPECL

1.5

2.5V

LVCMOS 2.5V, GTL+ 2.5V, LVDS2

1.0

2.5V

LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS2

1.25

1.8V

LVCMOS 1.8V

N/A

1.5V

LVCMOS 1.5V, HSTL Class I

0.75

Notes:

1. VCCI is used for both inputs and outputs

2. VCCI tolerance is ±5%

AX2000-1CSG896 Datasheet(PDF) 26 Page - Actel Corporation

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