AX2000-1CSG896 datasheet(24/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 10

v2.7

JTAG/Probe Pins

PRA/B/C/D

Probe A/B/C/D

The Probe pins are used to output data from any user-

defined design node within the device (controlled with

Silicon Explorer II). These independent diagnostic pins

can be used to allow real-time diagnostic output of any

signal

path

within

the

device.

The

pins’

probe

capabilities can be permanently disabled to protect

programmed design confidentiality. The probe pins are

of LVTTL output levels.

TCK

Test Clock

Test clock input for JTAG boundary-scan testing and

diagnostic probe (Silicon Explorer II).

TDI

Test Data Input

Serial

input

for

JTAG

boundary-scan

testing

and

diagnostic probe. TDI is equipped with an internal 10 k

pull-up resistor.

TDO

Test Data Output

Serial output for JTAG boundary-scan testing.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1

boundary-scan pins (TCK, TDI, TDO, TRST). TMS is

equipped with an internal 10 k

Ω pull-up resistor.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to

asynchronously initialize or reset the boundary scan circuit.

The TRST pin is equipped with a 10 k

Ω pull-up resistor.

Special Functions

Low Power Pin

The LP pin controls the low power mode of Axcelerator

devices. The device is placed in the low power mode by

connecting the LP pin to logic high. To exit the low

power mode, the LP pin must be set Low. Additionally,

the LP pin must be set Low during chip powering-up or

chip powering-down operations. See "Low Power

Mode" on page 2-89 for more details.

No Connection

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

User I/Os2

Introduction

The Axcelerator family features a flexible I/O structure,

supporting a range of mixed voltages (1.5V, 1.8V, 2.5V,

and 3.3V) with its bank-selectable I/Os. Table 2-8 on

page 2-11 contains the I/O standards supported by the

Axcelerator

family,

and

Table 2-10

page 2-11

compares the features of the different I/O standards.

Each I/O provides programmable slew rates, drive

strengths, and weak pull-up and weak pull-down circuits.

I/O standards, except 3.3V PCI and 3.3V PCI-X, are

capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V

tolerant with the aid of an external resistor.

The input buffer has an optional user-configurable delay

element. The element can reduce or eliminate the hold

time requirement for input signals registered within the

I/O cell. The value for the delay is set on a bank-wide

basis. Note that the delay WILL be a function of process

variations as well as temperature and voltage changes.

Each I/O includes three registers: an input (InReg), an

output (OutReg), and an enable register (EnReg). I/Os are

organized into banks, and there are eight banks per

device — two per side (Figure 2-6 on page 2-15). Each I/O

bank has a common VCCI, the supply voltage for its I/Os.

For voltage-referenced I/Os, each bank also has a

common reference-voltage bus, VREF. While VREF must

have a common voltage for an entire I/O bank, its

location is user-selectable. In other words, any user I/O in

the bank can be selected to be a VREF.

The location of the VREF pin should be selected according

to the following rules:

•

Any pin that is assigned as a VREF can control a

maximum of eight user I/O pad locations in each

direction (16 total maximum) within the same I/O

bank.

•

I/O pad locations listed as no connects are counted

as part of the 16 maximum. In many cases, this

leads to fewer than eight user I/O package pins in

each direction being controlled by a VREF pin.

•

Dedicated I/O pins (GND, VCCI...) are counted as

part of the 16.

•

The two user I/O pads immediately adjacent on each

side of the VREF pin (four in total) may only be used

as an input. The exception is when there is a VCCI/

GND pair separating the VREF pin and the user I/O

pad location.

2. Do not use an external resister to pull the I/O above VCCI for a higher logic “1” voltage level. The desired higher logic “1”

voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.

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