AX2000-1CSG896 datasheet(12/226 Pages) ACTEL

12 / 226 page

Axcelerator Family FPGAs

1- 6

v2.7

operating with input frequencies ranging from 14 MHz

to 200 MHz and can generate output frequencies

between 20 MHz and 1 GHz. The clock can be either

divided or multiplied by factors ranging from 1 to 64.

Additionally, multiply and divide settings can be used in

any combination as long as the resulting clock frequency

is between 20 MHz and 1 GHz. Adjacent PLLs can be

cascaded to create complex frequency combinations.

The PLL can be used to introduce either a positive or a

negative clock delay of up to 3.75 ns in 250 ps

increments. The reference clock required to drive the PLL

can be derived from three sources: external input pad

(either single-ended or differential), internal logic, or the

output of an adjacent PLL.

Low Power (LP) Mode

The AX architecture was created for high-performance

designs but also includes a low power mode (activated via

the LP pin). When the low power mode is activated, I/O

banks can be disabled (inputs disabled, outputs tristated),

and PLLs can be placed in a power-down mode. All

internal register states are maintained in this mode.

Furthermore, individual I/O banks can be configured to

opt out of the LP mode, thereby giving the designer access

to critical signals while the rest of the chip is in low power

mode.

The power can be further reduced by providing an

external voltage source (VPUMP) to the device to bypass

the internal charge pump (See "Low Power Mode" on

page 2-89 for more information).

Design Environment

The Axcelerator family of FPGAs is fully supported by both

Actel's Libero™ Integrated Design Environment and

Designer FPGA Development software. Actel Libero IDE is

an integrated design manager that seamlessly integrates

design tools while guiding the user through the design

flow, managing all design and log files, and passing

necessary design data among tools. Additionally, Libero

IDE allows users to integrate both schematic and HDL

synthesis into a single flow and verify the entire design in

a single environment (see the Libero IDE Flow diagram

located on Actel’s website). Libero IDE includes Synplify®

Actel Edition (AE) from Synplicity®, ViewDraw® AE from

Mentor Graphics®, ModelSim® HDL Simulator from

Mentor

Graphics,

WaveFormer

Lite™

from

SynaptiCAD®, and Designer software from Actel.

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

the following:

•

Timer – a world-class integrated static timing analyzer

and constraints editor which support timing-driven

place-and-route

•

NetlistViewer – a design netlist schematic viewer

•

ChipPlanner – a graphical floorplanner viewer and editor

•

SmartPower – allows the designer to quickly estimate

the power consumption of a design

•

PinEditor – a graphical application for editing pin

assignments and I/O attributes

•

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

Figure 1-8 • AX Routing Structures

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