AX2000-1CSG896 datasheet(18/226 Pages) ACTEL

18 / 226 page

Axcelerator Family FPGAs

2- 4

v2.7

Ptotal = Pdc + Pac

PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs

PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs

PR-cells = P7 * ms * Fs

PC-cells = P8 * mc * Fs

Pinputs = P9 * pi * Fpi

Poutputs = PI/O * po * Fpo

Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK

PPLL = P13 * FCLK

Pdc =ICCA * VCCA

Pac =PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL

= the number of R-cells clocked by this clock

= the clock frequency

= the number of R-cells clocked by this clock

= the clock frequency

the number of R-cells switching at each Fs cycle

the clock frequency

mc =

the number of C-cells switching at each Fs cycle

the clock frequency

= the number of inputs

Fpi = the average input frequency

Cload = the output load (technology dependent)

VCCI

= the output voltage (technology dependent)

= the number of outputs

Fpo

= the average output frequency

Nblock = the number of RAM/FIFO blocks (1 block = 4k)

FRCLK = the read-clock frequency of the memory

FWCLK = the write-clock frequency of the memory

FRefCLK = the clock frequency of the clock input of the PLL

FCLK

= the clock frequency of the first clock output of the PLL

AX2000-1CSG896 Datasheet(PDF) 18 Page - Actel Corporation