LTC1272-8ACSW datasheet(7/20 Pages) LINER

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LTC1272

1272fb

APPLICATI

I FOR ATIO

Conversion Details

Conversion start is controlled by the CS, RD and HBEN

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset and the three-state data

outputs are enabled. Once a conversion cycle has begun

it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, the AIN input connects to the sample-and-hold

capacitor through a 300

Ω/2.7kΩ divider. The voltage

divider allows the LTC1272 to convert 0V to 5V input

signals while operating from a 4.5V supply. The conver-

sion has two phases: the sample phase and the convert

phase. During the sample phase, the comparator offset is

nulled by the feedback switch and the analog input is

stored as a charge on the sample-and-hold capacitor,

CSAMPLE. This phase lasts from the end of the previous

conversion until the next conversion is started. A mini-

mum delay between conversions (t10) of 1µs allows

enough time for the analog input to be acquired. During the

convert phase, the comparator feedback switch opens,

putting the comparator into the compare mode. The

sample-and-hold capacitor is switched to ground inject-

ing the analog input charge onto the comparator summing

junction. This input charge is successively compared to

binary weighted charges supplied by the capacitive DAC.

Bit decisions are made by the comparator (zero crossing

detector) which checks the addition of each successive

weighted bit from the DAC output. The MSB decision is

made 50ns (typically) after the second falling edge of CLK

IN following a conversion start. Similarly, the succeeding

bit decisions are made approximately 50ns after a CLK IN

edge until the conversion is finished. At the end of a

conversion, the DAC output balances the AINoutputcharge.

The SAR contents (12-bit data word) which represent the

AIN input signal are loaded into a 12-bit latch.

Sample-and-Hold and Dynamic Performance

Traditionally A/D converters have been characterized by

such specs as offset and full-scale errors, integral

Figure 1. AIN Input

Figure 2. LTC1272 Non-Averaged, 1024 Point FFT Plot.

fS = 250kHz, fIN = 10kHz

VDAC

LTC1272 • TA07

–

CDAC

DAC

300

Ω

SAMPLE

HOLD

CSAMPLE

2.7k

AIN

12-BIT

LATCH

COMPARATOR

SAMPLE

FREQUENCY (kHz)

–110

–90

–70

–50

–30

–10

120

LTC1272 • TA23

–20

–40

–60

–80

–100

100

nonlinearity and differential nonlinearity. These specs are

useful for characterizing an ADC’s DC or low frequency

signal performance.

These specs alone are not adequate to fully specify the

LTC1272 because of its high speed sampling ability. FFT

(Fast Fourrier Transform) test techniques are used to

characterize the LTC1272’s frequency response, distor-

tion and noise at the rated throughput.

By applying a low distortion sine wave and analyzing the

digital output using a FFT algorithm, the LTC1272’s spec-

tral content can be examined for frequencies outside the

fundamental. Figure 2 shows a typical LTC1272 FFT plot.

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