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LTC1272

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APPLICATI

I FOR ATIO

Data Format

The output data format can be either a complete parallel

load for 16-bit microprocessors or a two byte load for

8-bit microprocessors. Data is always right justified (i.e.,

LSB is the most right-hand bit in a 16-bit word). For a two

byte read, only data outputs D7. . . D0/8 are used. Byte

selection is governed by the HBEN input which controls an

internal digital multiplexer. This multiplexes the 12 bits of

conversion data onto the lower D7. . . D0/8 outputs

(4MSBs or 8LSBs) where it can be read in two read cycles.

The 4MSBs always appear on D11 . . . D8 whenever the

three-state output drives are turned on.

Slow Memory Mode, Parallel Read (HBEN = Low)

Figure 14 and Table 2 show the timing diagram and data

bus status for Slow Memory Mode, Parallel Read. CS and

RD going low triggers a conversion and the LTC1272

acknowledges by taking BUSY low. Data from the previous

conversion appears on the three-state data outputs. BUSY

returns high at the end of conversion when the output

latches have been updated and the conversion result is

placed on data outputs D11 . . . D0/8.

Slow Memory Mode, Two Byte Read

For a two byte read, only 8 data outputs D7 . . . D0/8 are

used. Conversion start procedure and data output status

for the first read operation is identical to Slow Memory

Mode, Parallel Read. See Figure 15 timing diagram and

Table 3 data bus status. At the end of conversion the low

data byte (DB7 . . . DB0) is read from the ADC. A second

Read operation with HBEN high, places the high byte on

data outputs D3/11 . . . D0/8 and disables conversion start.

Note the 4MSBs appear on data outputs D11 . . . D8 during

the two Read operations above.

ROM Mode, Parallel Read (HBEN = Low)

The ROM Mode avoids placing a microprocessor into a

Wait state. A conversion is started with a Read operation

and the 12 bits of data from the previous conversion is

available on data outputs D11 . . . D0/8 (see Figure 16 and

Table 4). This data may be disregarded if not required. A

second Read operation reads the new data (DB11 . . . DB0)

and starts another conversion. A delay at least as long as

the LTC1272 conversion time plus the 1

µsminimumdelay

between conversions must be allowed between Read

operations.

Figure 14. Slow Memory Mode, Parallel Read Timing Diagram

Table 2. Slow Memory Mode, Parallel Read Data Bus Status

Data Outputs

D11

D10

D3/11

D2/10

D1/9

D0/8

Read

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

t11

t10

t12

tCONV

OLD DATA

DB11-DB0

NEW DATA

DB11-DB0

TRACK

HOLD

DATA

BUSY

LTC1272 • TA16

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