19

LTC1272

1272fb

Figure 23. Plugging the LTC1272 into an AD7572 Socket

Case 2: Clock Not Synchronous with CS and RD

S

APPLICATI

I FOR ATIO

EXTERNAL

ASYNCHRONOUS

CLOCK

10 F

µ

IN

REF

D11 (MSB)

D10

D9

D8

D7

CLK IN

CLK OUT

HBEN

RD

CS

BUSY

NC

V

LTC1272

D6

D5

D4

DGND

D3/11

D2/10

D1/9

D0/8

A

V

AGND

DD

✝

P

CONTROL

LINES

µ

µ

0.1 F

–15V

P

DATA

BUS

ANALOG INPUT

(0V TO 5V)

10

µF

THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V

REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER

OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE

10

RESISTOR.

Ω

*

THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE

ADC CLK

SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH

AN ASYNCHRONOUS CLOCK.

**

THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES

NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.

LTC1272 • TA05

2.42V

V

OUTPUT

*

REF

10

Ω

0.1

µF

10 F

µ

µ

0.1 F

5V

+

✝

OUT

74HC04

RD

S

Q

D**

CLK

1/2

74HC74

OR

µ

+

*

†

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.