HC210 datasheet(85/228 Pages) ALTERA

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Altera Corporation

4–43

September 2008

External Memory Interface Specifications

Tables 4–45 through 4–51 contain HardCopy II device specifications for

the dedicated circuitry used for interfacing with external memory

devices.

Table 4–46 lists the maximum delay in the fast timing model for the

HardCopy II DQS delay buffer. Multiply the number of delay buffers that

you are using in the DQS logic block to get the maximum delay

achievable in your system. For example, if you implement a 90° phase

shift at 200 MHz, you use three delay buffers in mode 2. The maximum

achievable delay from the DQS block is then 3 × .416 ps = 1.248 ns.

Table 4–45. DLL Frequency Range Specifications

Frequency Mode

Frequency Range

Resolution (Degrees)

100 to 175

150 to 230

22.5

200 to 310

240 to 350

Table 4–46. DQS Delay Buffer Maximum Delay in Fast Timing Model

DLL Frequency Mode

Maximum Delay Per Delay Buffer

Unit

0.833

1, 2, 3

0.416

Table 4–47. DQS Period Jitter Specifications for DLL-Delayed Clock

(tDQS_JITTER)

Note (1)

Number of DQS Delay Buffer

Stages (2)

Commercial

Industrial

Unit

110

130

180

160

210

Notes to Table 4–47:

(1)

Peak-to-peak period jitter on the phase shifted DQS clock.

(2)

Delay stages used for requested DQS phase shift are reported in your project’s

Compilation Report in the Quartus II software.

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