HC210 datasheet(19/228 Pages) ALTERA

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Altera Corporation

2–11

September 2008

Preliminary

PLLs and Clock Networks

Enhanced and Fast PLLs

The number of PLLs available differs based on density (Table 2–5).

The target HardCopy II device may not support the same number of

enhanced PLLs as the prototyping Stratix II FPGA. However, since

HardCopy II enhanced PLLs and fast PLLs offer a similar feature set

(Table 2–7 on page 2–13), a fast PLL could be used in place of an enhanced

PLL. The type of PLL used in the design should be chosen using the

Quartus II software to accommodate the resources available in the

HardCopy II device.

Table 2–6 shows which PLLs are available in each device density.

Figure 2–3 shows the location of each PLL. During the prototyping stage

using the FPGA, you must select the appropriate number of enhanced

and fast PLLs that will be used in your HardCopy II device. Use Table 2–6

to ensure that the FPGA prototyping design uses the same PLL resources

available in the HardCopy II device.

Note to Table 2–4:

(1)

Maximum performance information is preliminary until device characterization.

(2)

The memory cells power up randomly, so reads before writes are not valid. Make sure you write to the memory

location before you read it.

(3)

Even though the output register is cleared, the memory cells power up randomly. So reads before write are not

valid. Make sure you write to the memory location first before reading it.

(4)

Violating the setup or hold time requirements on the address registers could corrupt the memory contents. This

applies to both read and write operations.

Table 2–4. HardCopy II Embedded Memory Features

(Part 2 of 2) Notes (1), (2), (3)

Feature

M4K Blocks

M-RAM Blocks

Table 2–5. HardCopy II PLLs

Feature

HC210W

HC210

HC220

HC230

HC240

Enhanced PLLs

22244

Fast PLLs

22248

Table 2–6. HardCopy II PLLs Available

(Part 1 of 2)

Note (1)

Device

Fast PLLs

Enhanced PLLs

234

HC210W

HC210

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