UM0470 datasheet(32/37 Pages) STMICROELECTRONICS

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Debug module (DM)

UM0470

32/37

4.12.9

DM control/status register 1 (DM_CSR1)

Address: 7F98h

Reset value: 0001 0000 (10h)

765

432

Reserved

STE

STF

RST

BRW

BK2F

BK1F

Reserved

rrr

Bit 7

Reserved.

Bit 6

STE Step mode enable (Read / Write)

This bit is set and cleared by software. It enables Step mode.

0: Step mode disabled

1: Step mode enabled

Bit 5

STF Step Flag (Read Only)

This bit indicates that the stall was generated by Step mode. It is set and cleared by

hardware. Writing to this bit does not change the bit value.

0: Step mode stall did not occur

1: Step mode stall occurred

Bit 4

RST Reset Flag (Read Only)

This bit is set by hardware when the CPU was stalled by the debug module (DM),

just after reset. It is cleared by hardware when the STALL bit is cleared. Writing to

this bit does not change the bit value.

0: No reset occurred

1: A reset occurred

Bit 3

BRW Break on Read/Write Flag (Read Only).

This bit gives the value of the read/write signal when a break occurs. Its value is not

significant for instruction fetch breaks. It is set by hardware depending on the

breakpoint conditions (see Table 4: Decoding table for breakpoint interrupt

generation on page 20) and is cleared by hardware depending on the next

breakpoint conditions. Writing to this bit does not change the bit value.

0: Breakpoint on write

1: Breakpoint on read

Bit 2

BK2F Breakpoint 2 Flag (Read Only).

This bit indicates that the DM stall was generated by Breakpoint 2. It is set by

hardware depending on the control conditions (see Table 4: Decoding table for

breakpoint interrupt generation on page 20) and is cleared by hardware when the

STALL bit is cleared. Writing to this bit does not change the bit value.

0: Breakpoint 2 did not occur

1: Breakpoint 2 occurred

Bit 1

BK1F Breakpoint 1 Flag (Read Only).

This bit indicates that the DM interrupt was generated by Breakpoint 1. It is set by

hardware depending on the control conditions (see Table 4: Decoding table for

breakpoint interrupt generation on page 20) and is cleared by hardware when the

STALL bit is cleared. Writing to this bit does not change the bit value.

0: Breakpoint 1 did not occur

1: Breakpoint 1 occurred

Bit 0

Reserved

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