TMS320UC5402 datasheet(34/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multiply-by-N clock option

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate

the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator

section.

When an external clock source is used, the external frequency injected must conform to specifications listed

in the timing requirements table.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

switching

characteristics

over

recommended

operating

conditions

0.5tc(CO)]

(see Figure 9 and Figure 11)

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

12.5

tc(CI)/N†

td(CI-CO)

Delay time, X2/CLKIN high/low to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high

H–2

H–1

Transitory phase, PLL lock up time

† N = Multiplication factor

timing requirements (see Figure 11)†

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1–15)

12.5N

400N

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.5

12.5N

200N

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.25, x.75

12.5N

100N

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

† N = Multiplication factor

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

X2/CLKIN

CLKOUT

td(CI-CO)

tw(COL)

tr(CI)

Unstable

Figure 11. External Multiply-by-One Clock Timing

TMS320UC5402 Datasheet(PDF) 34 Page - Texas Instruments

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