TMS320UC5402 datasheet(8/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTION

TYPE†

TERMINAL

NAME

DESCRIPTION

TYPE†

PLL/TIMER SIGNALS (CONTINUED)

CLKMD1

CLKMD2

CLKMD3

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The

logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select

signals have no effect until the device is reset again.

X2/CLKIN‡

Clock/PLL input. If the internal oscillator is not being used, this X2/CLKIN functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.

TOUT0

O/Z

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT

cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.

TOUT1

O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one

CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0

BCLKR1

I/O/Z

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

Serial data receive input

BFSR0

BFSR1

I/O/Z

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0

BCLKX1

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when

EMU1/OFF goes low.

BDX0

BDX1

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

asserted, or when EMU1/OFF is low.

BFSX0

BFSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX

can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the

high-impedance state when EMU1/OFF is low.

MISCELLANEOUS SIGNAL

No connection

HOST-PORT INTERFACE SIGNALS

HD0–HD7

I/O/Z

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the

HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the

high-impedance state when not outputting data or when EMU1/OFF is low. The HPI data bus includes bus

holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not

being driven by the ’UC5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders

are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

HCNTL0

HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have

internal pullup resistors that are only enabled when HPIENA = 0.

HBIL

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup

resistor that is only enabled when HPIENA = 0.

HCS

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input

has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1

HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs

have internal pullup resistors that are only enabled when HPIENA = 0.

HAS

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA

† I = input, O = output, Z = high impedance, S = supply

‡ If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

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