TMS320UC5402 datasheet(17/63 Pages) TI

17 / 63 page

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

enhanced 8-bit host-port interface (HPI-8) (continued)

The HPI-8 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5402.

A major enhancement to the ’UC5402 HPI over previous versions is that it allows host access to the entire

on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and

host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the

same location, the host has priority, and the DSP waits for one HPI-8 cycle. Note that since host accesses are

always synchronized to the ’UC5402 clock, an active input clock (CLKIN) is required for HPI-8 accesses during

IDLE states, and host accesses are not allowed while the ’UC5402 reset pin is asserted.

The HPI-8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers

are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with

the HPI-8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an

HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register

is accessible by both the host and the ’UC5402.

multichannel buffered serial ports

The ’UC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that

allow direct interface to other ’C54x/’LC54x DSPs, codecs, and other devices in a system. The McBSPs are

based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP

provides:

D Full-duplex communication

D Double-buffered data registers, which allow a continuous data stream

D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

–

T1/E1 framers

–

MVIP switching compatible and ST-BUS compliant devices

–

IOM-2 compliant devices

–

Serial peripheral interface devices

D Multichannel transmit and receive of up to 128 channels

D A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

D µ-law and A-law companding

D Programmable polarity for both frame synchronization and data clocks

D Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external

interface of each McBSP consists of the following pins:

D BCLKX

Transmit reference clock

D BDX

Transmit data

D BFSX

Transmit frame synchronization

D BCLKR

Receive reference clock

D BDR

Receive data

D BFSR

Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family

of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX

pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register

(DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure

allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

TMS320UC5402 Datasheet(PDF) 17 Page - Texas Instruments

TMS320UC5402 Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL