TMS77C82 datasheet(10/49 Pages) TI

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

program EPROM

The TMS370C702 device contains 8K bytes of EPROM, mapped, at location 6000h and continuing through

location 7FFFh as shown in Figure 3. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and

reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses

7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During

programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module

features include:

D Programming

–

In-circuit programming capability if VPP is applied to MC

–

Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 5.

D Write protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset halts all programming to the EPROM module.

–

Low-power modes

–

13 V not applied to MC

program ROM

The program read-only memory (ROM) consists of 8K bytes of mask-programmable ROM. The program ROM

is used for permanent storage of data or instructions. Memory addresses 7FF0h through 7FFFh are reserved

for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located

between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device

fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system reset operation ensures an orderly start-up sequence for the TMS370Cx0x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

internally generated, while one (RESET pin) is controlled externally. These actions are as follows:

D External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

TMS370

Family User’s Guide (literature number SPNU127) for more information.

D Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x0x device to reset external system components. Additionally, if a cold start (VCC is off

for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

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