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TMS77C82 Datasheet(PDF) 37 Page - Texas Instruments |
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TMS77C82 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 49 page  TMS370Cx0x 8-BIT MICROCONTROLLER SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 17. Peripheral File Frame Compilation (Continued) PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Capture / Compare (Continued) P044 Bit 15 Capture/Compare Register MSbyte Bit 8 T1CC P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 7 Watchdog Reset Key Bit 0 WDRST P049 WD OVRFL TAP SEL† WD INPUT SELECT2† WD INPUT SELECT1† WD INPUT SELECT0† — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD OVRFL INT FLAG T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE=0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 Mode: Capture / Compare P04B T1EDGE INT FLAG — T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 P04C T1 MODE = 1 T1C1 OUT ENA — T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Modes: Dual-Compare and Capture / Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI SCI1 Module Control Memory Map P050 STOP BITS EVEN/ODD PARITY PARITY ENABLE ASYNC/ ISOSYNC ADDRESS/ IDLE WUP SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR P051 — — SCI SW RESET CLOCK TXWAKE SLEEP TXENA RXENA SCICTL P052 BAUDF (MSB) BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD MSB P053 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 (LSB) BAUD LSB P054 TXRDY TX EMPTY — — — — — SCI TX INT ENA TXCTL P055 RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCI RX INT ENA RXCTL P056 Reserved P057 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 RXBUF P058 Reserved † Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. |
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