TMS77C82 datasheet(23/49 Pages) TI

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programmable timer 1 (continued)

The TMS370Cx0x device includes a 24-bit watchdog (WD) timer, contained in the timer 1 module, which can

be programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not used.

The WD function is to monitor software and hardware operation and to implement a system reset when the WD

counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The

WD can be configured as one of three mask options as follows:

D Standard watchdog configuration (see Figure 8) – for EPROM and mask-ROM devices:

–

Watchdog mode

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

–

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

–

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog mode

–

Watchdog timer can be configured as an event counter, a pulse accumulator, or an interval timer

16-Bit

WatchdogCounter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard watchdog

TMS77C82 Datasheet(PDF) 23 Page - Texas Instruments

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