TMS370Cx1x

8-BIT MICROCONTROLLER

SPNS012F – MAY 1987 – REVISED FEBRUARY 1997

41

POST OFFICE BOX 1443

external clocking requirements for clock divided by 4 (see Note 10 and Figure 19)

NO.

PARAMETER

MIN

MAX

UNIT

1

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 11)

20

ns

2

tr(Cl)

Rise time, XTAL2/CLKIN

30

ns

3

tf(CI)

Fall time, XTAL2/CLKIN

30

ns

4

td(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall

100

ns

CLKIN

Crystal operating frequency

2

20

MHz

SYSCLK

Internal system clock operating frequency†

0.5

5

MHz

† SYSCLK = CLKIN/4

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

11. This pulse may be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

3

2

1

4

SYSCLK

Figure 19. External Clock Timing for Divide-by-4

external clocking requirements for clock divided by 1 (PLL) (see Note 10 and Figure 20)

NO.

PARAMETER

MIN

MAX

UNIT

1

tw(Cl)

Pulse duration, XTAL2/CLKIN (see Note 11)

20

ns

2

tr(Cl)

Rise time, XTAL2/CLKIN

30

ns

3

tf(CI)

Fall time, XTAL2/CLKIN

30

ns

4

td(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise

100

ns

CLKIN

Crystal operating frequency

2

5

MHz

SYSCLK

Internal system clock operating frequency‡

2

5

MHz

‡ SYSCLK = CLKIN/1

NOTES: 10. For VIL and VIH, refer to recommended operating conditions.

11. This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

4

3

2

1

XTAL2/CLKIN

SYSCLK

Figure 20. External Clock Timing for Divide-by-1