LTC6412CUFPBF datasheet(16/24 Pages) LINER

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LTC6412

6412f

APPLICATIONS INFORMATION

must be within 100mV of VCC. The Exposed Pad on the

underside of the package must be connected to ground

with low inductance and low thermal resistance. Refer to

details of DC1464A (Test Circuit A) for an example of proper

grounding and supply decoupling. Failure to provide low

impedance supply and ground at high frequencies can

cause oscillations and increased distortion.

Enable/Shutdown

Both the EN pin and SHDN pin are self-biased to VCC

through their respective 100k pull-up resistors, so the

default open-pin state is powered on with the output ampli-

ﬁer signal path disabled. Pulling the EN pin low completes

the signal path from the attenuator ladder through the

output ampliﬁer. The EN pin essentially provides a fast

muting function while the SHDN pin provides slower

power on/off function.

For applications requiring the SHDN function, it is recom-

mended that the output ampliﬁer signal path be disabled

with a high EN voltage before transitioning the SHDN

signal. When enabling the ampliﬁer, allow at least 5ms

dwell time between the rising SHDN transition and the

falling EN transition to avoid non-monotonic output signal

behavior though the VGA. The opposite delay sequence

is recommended for the falling SHDN transition, but this

is less critical as the output signal amplitude will drop

abruptly regardless of the EN pin.

SHDN

tDWELL

6412 AI01

Layout/Grounding

The high frequency performance of the LTC6412 requires

special attention to proper RF grounding, bias decoupling

and termination. The recommended PCB stack-up for a

4-layer board is shown below for 1oz copper clad FR-4

laminate with a relative dielectric constant,

εr = 4.2-4.5

at 1GHz.

METAL 1

METAL 2

METAL 3

METAL 4

RF SIGNAL

FR4 12-18 MILS

FR4 20-30 MILS

FR4 NOT CRITICAL

GROUND PLANE

POWER PLANE

GND AND LF SIGNAL

6412 AI02

The topside metal and silkscreen drawings for Test Circuit A

illustrate the recommended decoupling capacitor place-

ment, signal routing and grounding. Ground vias directly

beneath the Exposed Pad are critical; use as many as

possible. Ground vias to the other ground pins are less

critical.

ESD

The LTC6412 is protected with reverse-biased ESD diodes

on all I/O pins. If any I/O pin is forced one diode drop above

the positive supply or one diode drop below the negative

supply, then large currents may ﬂow through the diodes.

No damage to the devices will occur if the current is kept

below 10 mA. The +OUT/–OUT pins have additional series

diodes to the positive supply and can sustain approximately

2V overshoot above the positive supply before conducting

appreciable currents.

LTC6412CUFPBF Datasheet(PDF) 16 Page - Linear Technology

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