TMC22X5YA datasheet(5/84 Pages) CADEKA

5 / 84 page

PRODUCT SPECIFICATION

TMC22x5yA

REV. 1.0.0 2/4/03

assumed to be luminance and the high frequency portion is

processed as chrominance to ﬁnd the magnitude and phase of

the chrominance vector. These three components are then

compared across the (0H & 1H) and (1H & 2H) taps of the

comb ﬁlter to produce the difference in luminance, chromi-

nance magnitude, and chrominance phase. These differences

are then translated in the user-programmable lookup table to

produce the “K” signal which controls the complementary

mix between the output of the comb ﬁlter and the simple

bandsplit decoder. That is, the “K” signals controls how

much of the combed high frequency luminance signal is sub-

tracted from the simple bandsplit chrominance for chroma

combs, or added to the low frequency output of the bandsplit

for luma comb ﬁlters.

Output Processor

The demodulated chrominance signal and the luminance

signal are passed through a programmable output matrix,

producing RGB, YUV, or YCBCR. When the clock is at

27MHz, a D1 signal can be produced on the R/V output with

the embedded TRS words ﬁxed to the external HSYNC and

VSYNC timing.

Parallel and Serial Microprocessor Interfaces

The parallel microprocessor interface employs 12 pins, the

serial port uses 5. A single pin, SER, selects between the two

interface modes.

In parallel interface mode, one address line is decoded for

access to the internal control register and its pointer.

Controls are reached by loading a desired address through

the 8-bit D7-0 port, followed by the desired data (read or

write) for that address. The control register address pointer

auto-increments to address 3Fh and then remains there.

A 2-line serial interface may also be used for initialization

and control. The same set of registers accessed by the paral-

lel port is available to the serial port. The device address in

the serial interface is selected via pins SA2-0.

The RESET pin sets all internal state machines to their ini-

tialized conditions and places the decoder in a power-down

mode. All register data are maintained while in power-down

mode.

Pin Assignments

G/Y1

G/Y0

LDV

GND

VDD

B/Cb9

B/Cb8

B/Cb7

B/Cb6

B/Cb5

B/Cb4

B/Cb3

B/Cb2

B/Cb1

B/Cb0

GND

VDD

R/Cr9

R/Cr8

R/Cr7

R/Cr6

R/Cr5

R/Cr4

R/Cr3

R/Cr2

R/Cr1

R/Cr0

GND

VDD

DREF

FID0

FID1

FID2

DHSYNC

DVSYNC

GND

VDD

GND

VDD

HSYNC

VSYNC

BUFFER

Pin Name

RESET

SET

SER

SA0

SA1

SA2

GND

SDA

SCL

R/W

GND

VDD

VIDEOB0

VIDEOB1

VIDEOB2

VIDEOB3

VIDEOB4

VIDEOB5

VIDEOB6

VIDEOB7

VIDEOB8

VIDEOB9

GND

VIDEOA0

VIDEOA1

VIDEOA2

VIDEOA3

VIDEOA4

VIDEOA5

VIDEOA6

VIDEOA7

VIDEOA8

VIDEOA9

MASTER0

MASTER1

CLOCK

GND

VDD

GND

G/Y9

G/Y8

G/Y7

G/Y6

G/Y5

G/Y4

G/Y3

G/Y2

100

Pin Name

Name

65-22x5y-03

100

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