PIC18F4321 datasheet(38/402 Pages) MICROCHIP

38 / 402 page

PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 38

3.8

Effects of Power-Managed Modes

on the Various Clock Sources

When PRI_IDLE mode is selected, the designated pri-

mary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator

using the OSC1 pin is disabled. The OSC1 pin (and

OSC2 pin in Crystal Oscillator modes) will stop

oscillating.

secondary

clock

modes

(SEC_RUN

and

SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),

the internal oscillator block provides the device clock

source. The 31 kHz INTRC output can be used directly

to provide the clock and may be enabled to support

various special features, regardless of the power-

managed mode (see Section 24.2 “Watchdog Timer

(WDT)”, Section 24.3 “Two-Speed Start-up” and

Section 24.4 “Fail-Safe Clock Monitor” for more

information). The INTOSC output at 8 MHz may be

used directly to clock the device or may be divided

down by the postscaler. The INTOSC output is disabled

if the clock is provided directly from the INTRC output.

The INTOSC output is also enabled for Two-Speed

Start-up at 1 MHz after a Reset.

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a Real-

Time Clock. Other features may be operating that do

not require a device clock source (i.e., MSSP slave,

PSP, INTx pins and others). Peripherals that may add

significant

current

consumption

are

listed

Section 27.2 “DC Characteristics”.

3.9

Power-up Delays

Power-up delays are controlled by two or three timers,

so that no external Reset circuitry is required for most

applications. The delays ensure that the device is kept

in Reset until the device power supply is stable under

normal circumstances and the primary clock is operat-

ing and stable. For additional information on power-up

delays, see Section 5.5 “Device Reset Timers”.

The first timer is the Power-up Timer (PWRT) which

provides a fixed delay on power-up (parameter 33,

Table 27-10). It is enabled by clearing (= 0) the

PWRTEN Configuration bit (CONFIG2L<0>).

3.9.1

DELAYS FOR POWER-UP AND

RETURN TO PRIMARY CLOCK

The second timer is the Oscillator Start-up Timer

(OST), intended to delay execution until the crystal

oscillator is stable (LP, XT and HS modes). The OST

does this by counting 1024 oscillator cycles before

allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, a third

timer delays execution for an additional 2 ms following

the HS mode OST delay, so the PLL can lock to the

incoming clock frequency. At the end of these delays,

the OSTS bit (OSCCON<3>) is set.

There is a delay of interval TCSD (parameter 38,

Table 27-10), once execution is allowed to start, when

the controller becomes ready to execute instructions.

This delay runs concurrently with any other delays.

This may be the only delay that occurs when any of the

EC, RC or INTIO modes are used as the primary clock

source.

TABLE 3-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode

OSC1 Pin

OSC2 Pin

RC, INTIO1

Floating, external resistor pulls high

At logic low (clock/4 output)

RCIO

Floating, external resistor pulls high

Configured as PORTA, bit 6

INTIO2

Configured as PORTA, bit 7

Configured as PORTA, bit 6

ECIO

Floating, driven by external clock

Configured as PORTA, bit 6

Floating, driven by external clock

At logic low (clock/4 output)

LP, XT and HS

Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

Note:

See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F4321 Datasheet(PDF) 38 Page - Microchip Technology

PIC18F4321 Datasheet(HTML) 38 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL