PIC18F4321 datasheet(69/402 Pages) MICROCHIP

69 / 402 page

DS39689F-page 69

PIC18F2221/2321/4221/4321 FAMILY

TABLE 6-2:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details on

page:

TOSU

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

55, 60

TOSH

Top-of-Stack High Byte (TOS<15:8>)

0000 0000

55, 60

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

0000 0000

55, 60

STKPTR

STKFUL(6)

STKUNF(6)

—

SP4

SP3

SP2

SP1

SP0

00-0 0000

55, 61

PCLATU

—

Holding Register for PC<21:16>

--00 0000

55, 60

PCLATH

Holding Register for PC<15:8>

0000 0000

55, 60

PCL

PC Low Byte (PC<7:0>)

0000 0000

55, 60

TBLPTRU

—

bit 21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000

55, 82

TBLPTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

55, 82

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000

55, 82

TABLAT

Program Memory Table Latch

0000 0000

55, 82

PRODH

Product Register High Byte

xxxx xxxx

55, 95

PRODL

Product Register Low Byte

xxxx xxxx

55, 95

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

55, 99

INTCON2

RBPU

INTEDG0

INTEDG1

INTEDG2

—TMR0IP

—RBIP

1111 -1-1

55, 100

INTCON3

INT2IP

INT1IP

—

INT2IE

INT1IE

—

INT2IF

INT1IF

11-0 0-00

55, 101

INDF0

Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)

N/A

55, 74

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)

N/A

55, 74

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)

N/A

55, 74

PREINC0

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)

N/A

55, 74

PLUSW0

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

value of FSR0 offset by W

N/A

55, 74

FSR0H

—

Indirect Data Memory Address Pointer 0 High Byte

---- 0000

55, 74

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx

55, 74

WREG

Working Register

xxxx xxxx

INDF1

Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)

N/A

55, 74

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)

N/A

55, 74

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)

N/A

55, 74

PREINC1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)

N/A

55, 74

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

value of FSR1 offset by W

N/A

55, 74

FSR1H

—

Indirect Data Memory Address Pointer 1 High Byte

---- 0000

56, 74

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

56, 74

BSR

—

Bank Select Register

---- 0000

56, 65

INDF2

Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)

N/A

56, 74

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)

N/A

56, 74

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)

N/A

56, 74

PREINC2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)

N/A

56, 74

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

value of FSR2 offset by W

N/A

56, 74

FSR2H

—

Indirect Data Memory Address Pointer 2 High Byte

---- 0000

56, 74

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

56, 74

STATUS

—

—N

---x xxxx

56, 72

Legend:

x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note

The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See

Section 5.4 “Brown-out Reset (BOR)”.

These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in

INTOSC Modes”.

The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is

read-only.

RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F4321 Datasheet(PDF) 69 Page - Microchip Technology

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