PIC18F4321 datasheet(92/402 Pages) MICROCHIP

92 / 402 page

PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 92

8.5

Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

Configuration

Words.

External

read

and

write

operations are disabled if code protection is enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 24.0

“Special Features of the CPU” for additional

information.

8.6

Protection Against Spurious Write

To protect against spurious EEPROM writes, various

mechanisms have been implemented. On power-up,

the WREN bit is cleared. In addition, writes to the

EEPROM are blocked during the Power-up Timer

period (TPWRT, parameter 33).

The write initiate sequence and the WREN bit together

help prevent an accidental write during Brown-out

Reset, power glitch or software malfunction.

8.7

Using the Data EEPROM

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing data. Such data is

typically updated at least one time within the number of

writes defined by specification, D124. If any location

storing data is not written at least this often, the data

EEPROM array must be refreshed. For this reason,

values that change infrequently, or not at all, should be

stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 8-3.

EXAMPLE 8-3:

DATA EEPROM REFRESH ROUTINE

Note:

If data EEPROM is only used to store con-

stants and/or data that changes often, an

array refresh is likely not required. See

specification, D124.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

LOOP

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

0AAh

;

MOVWF

EECON2

; Write 0AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

LOOP

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

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