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AT697F Datasheet(PDF) 146 Page - ATMEL Corporation |
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AT697F Datasheet(HTML) 146 Page - ATMEL Corporation |
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146 / 155 page  146 7703C–AERO–6/09 AT697F ADVANCE INFORMATION Differences between AT697F and AT697E This section summarizes the modifications, changes and improvements performed on the AT697F with regards to the AT697E. New/Modified Features Table 128. Summary of the new/modified features Feature AT697F AT697E Write protection scheme Start/End addresses and MASK based MASK based only BRDY* capability over ROM area Implemented Not Implemented Asynchronous BRDY* capability Implemented Not Implemented 16-bit wide memory bus support Not Implemented Implemented 32-bit timers and watchdog Implemented 24-bit only 8 external interrupts support Implemented limited to 4 PCI SYSEN* state visible in a register Implemented Not Implemented PCI configuration registers local read capability in satellite mode Implemented Not Implemented PCI double word transaction as two single transactions support Not Implemented Implemented AHB trace buffer freeze on debug mode entry Implemented Not Implemented In addition to the new/modified features presented in the above table, most of the functional bugs known from the AT697E model are corrected. Please refer to the AT697 errata sheet - 4409C-AERO-07/07 available at www.atmel.com for detailled information on the functional bugs status. Register modifications Table 129. Summary of the register changes Register Address AT697F Description AT697E Description MCFG1 0x80000000 bit 30 - PROM bus ready enable bit 29 - Asynchronous bus read enable bit 30 - reserved bit 29 -reserved WPSTA1 0x800000D0 Write Protection Start Address 1 register bit 29:2 - Start address bit 1 - Block protect mode enable not available WPSTO1 0x800000D4 Write Protection Stop Address 1 register bit 29:2 - Stop address bit 1 - User write protection enable bit 0 - Supervisor write protection enable not available WPSTA2 0x800000D8 Write Protection Start Address 2 register bit 29:2 - Start address bit 1 - Block protect mode enable not available WPSTO2 0x800000DC Write Protection Stop Address 2 register bit 29:2 - Stop address bit 1 - User write protection enable bit 0 - Supervisor write protection enable not available TIMC1 0x80000040 bit 31:0 - timer counter bit 24:0 - timer counter TIMR1 0x80000044 bit 31:0 - reload counter bit 24:0 - reload counter TIMC2 0x80000050 bit 31:0 - timer counter bit 24:0 - timer counter TIMR2 0x80000054 bit 31:0 - reload counter bit 24:0 - reload counter WDG 0x8000004C bit 31:0 - counter bit 24:0 - counter |
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