AT697F datasheet(52/155 Pages) ATMEL

52 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

PCI Interface

Overview

The PCI interface implementation is compliant with the PCI 2.2 specification. It is a high perfor-

mance 32-bit bus interface with multiplexed address and data lines. It is intended for use as an

interconnect mechanism between processor/memory systems and peripheral controller

components.

The AT697 processor embedds the In-Silicon PCI core. It is interfaced to the processor core

through the PCI to AMBA bridge developped by the European Space Agency.

The PCI bus operations can be clocked at a frequency up to 33MHz, independently of the pro-

cessor clock. Synchronization of the operation between PCI interface and AT697 core implies

numerous FIFO usage. This implementation allows to use the device for Initiator (Master) and

Target operations. In each mode single word and burst transfer can be executed.

Two different operating modes can be used with the PCI interface :

•

Host Bridge

The host-bridge connects the local bus of a processor to the PCI bus. Its PCI configuration

registers are accessible locally by the processor, but not through PCI configuration cycles.

Host-bridge initialises other satellite devices through PCI configuration commands.

•

Satellite

The satellite is a PCI device, configurable via PCI configuration cycles and the idsel line, but

not locally.

Both, host-bridge and satellites can be initiator and/or target on the bus. The present interface

has universal functionality, allowing both operation modes. The mode is configured via a hard-

ware bootstrap on the SYSEN* pin. The state of the SYSEN* pin is copied in PCIIS SYS. This

enables plug and play boot programs loading the appropriate driver depending on the hardware

configuration. In the same manner, the configuration registers are made visible as read only

when the device is configured as satellite

Some other features are supported by this interface like

•

Target lock support

•

Zero-latency Fast Back-to-Back transfers

•

Zero wait state burst mode transfers

•

Support for memory read line/multiple

•

Support for memory write and invalidate commands

•

Delayed read support

•

Flexible error reporting by polling

The PCI bus is a multiplexed one. In this way, address and data through the same medium. That

is why PCI communication is based on two phase burst transfer. Each transfer is composed of

the following phases :

•

An address phase

During the address phase, the initiator of the communication drives the 32-bit address

concerned by the transfer and the command involved through this transfer. The command

defines the space area concerned with the transfer and the direction of the transfer.

•

A data phase

During the data phase the initiator of the communication drives the enable bit signal so that

only active part of the bus is enabled. When reading, the initiator drives the enable bits and

the target set the data on the bus.

PCI Initiator

(Master)

The PCI initiator mode of the AT697 gives a direct memory-mapped (initiator) access to the PCI

bus. Any access to a memory address in the PCI address range is automatically translated by

the interface into the appropriate PCI transaction. In this configuration, the PCI bus is accessed

by the same instructions as the main memory. The SPARC instruction set foresees various

load/store instruction types. The PCI bus foresees 32 bit wide transactions with byte-enables for

each byte lane.

AT697F Datasheet(PDF) 52 Page - ATMEL Corporation

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