ATmega16U4 datasheet(85/408 Pages) ATMEL

85 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

11.0.2

External Interrupt Control Register B – EICRB

• Bit 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.

• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits

The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corre-

sponding interrupt mask in the EIMSK is set. The level and edges on the external pin that

activate the interrupt are defined in Table 11-3. The value on the INT6 pin are sampled before

detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock

period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.

Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is

enabled. If low level interrupt is selected, the low level must be held until the completion of the

currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will

generate an interrupt request as long as the pin is held low.

Note:

1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 11-1.

Interrupt Sense Control(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Table 11-2.

Asynchronous External Interrupt Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

tINT

Minimum pulse width for

asynchronous external interrupt

Bit

7654

ISC61

ISC60

EICRB

Read/Write

R/W

Initial Value

0000

Table 11-3.

Interrupt Sense Control

(1)

ISC61

ISC60

Description

The low level of INT6 generates an interrupt request.

Any logical change on INT6 generates an interrupt request

The falling edge between two samples of INT6 generates an interrupt

request.

The rising edge between two samples of INT6 generates an interrupt

request.

ATmega16U4 Datasheet(PDF) 85 Page - ATMEL Corporation

ATmega16U4 Datasheet(HTML) 85 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL