ATmega16U4 datasheet(89/408 Pages) ATMEL

89 / 408 page

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 4. Prescaler for synchronous Timer/Counters

Note:

T3 input is not available on the

ATmega16U4/ATmega32U4 products. “Tn” only refers to

either T0 or T1 inputs.

12.4

General Timer/Counter Control Register – GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be

Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note

that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset

of this prescaler will affect all timers.

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

Bit

TSM

–

PSRA-

PSRSY

GTCCR

Read/Write

R/W

Initial Value

ATmega16U4 Datasheet(PDF) 89 Page - ATMEL Corporation

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