R5F3650KDFB datasheet(97/112 Pages) RENESAS

97 / 112 page

REJ03B0257-0110 Rev.1.10 Sep 24, 2009

Page 97 of 109

M16C/65 Group

5. Electrical Characteristics

VCC1 = VCC2 = 3 V

5.3.4

Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)

(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)

5.3.4.1

In No Wait State Setting

Notes:

Calculated according to the BCLK frequency as follows:

f(BCLK) is 12.5 MHz or less.

Calculated according to the BCLK frequency as follows:

This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t =

−CR × ln(1 − V

OL/VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,

hold time of output low level is

t =

−30 pF × 1 kΩ × In(1 − 0.2V

CC2/VCC2)

= 6.7 ns.

Table 5.60

Memory Expansion and Microprocessor Modes (in No Wait State Setting)

Symbol

Parameter

Measuring

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See

Figure 5.27

th(BCLK-AD)

Address output hold time (in relation to BCLK)

0ns

th(RD-AD)

Address output hold time (in relation to RD)

0ns

th(WR-AD)

Address output hold time (in relation to WR)

(Note 2)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (in relation to BCLK)

0ns

td(BCLK-ALE)

ALE signal output delay time

th(BCLK-ALE)

ALE signal output hold time

−4ns

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

0ns

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

0ns

td(BCLK-DB)

Data output delay time (in relation to BCLK)

th(BCLK-DB)

Data output hold time (in relation to BCLK) (3)

0ns

td(DB-WR)

Data output delay time (in relation to WR)

(Note 1)

th(WR-DB)

Data output hold time (in relation to WR) (3)

(Note 2)

td(BCLK-HLDA)

HLDA output delay time

0.5

BCLK

()

----------------------40 ns

[]

–

0.5

BCLK

()

----------------------10 ns

[]

–

DBi

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