ATtiny261A datasheet(138/292 Pages) ATMEL

138 / 292 page

138

8197A–AVR–10/09

ATtiny261A/461A/861A

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 14-2.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

14.2.2

ACSRB – Analog Comparator Control and Status Register B

• Bit 7 – HSEL: Hysteresis Select

When this bit is written logic one, the hysteresis of the Analog Comparator is switched on. The

hysteresis level is selected by the HLEV bit.

• Bit 6 – HLEV: Hysteresis Level

When the hysteresis is enabled by the HSEL bit, the Hysteresis Level, HLEV, bit selects the hys-

teresis level that is either 20mV (HLEV=0) or 50mV (HLEV=1).

• Bit 2:0 – ACM2:ACM0: Analog Comparator Multiplexer

The Analog Comparator multiplexer bits select the positive and negative input pins of the Analog

Comparator. The different settings are shown in Table 14-1.

14.2.3

DIDR0 – Digital Input Disable Register 0

• Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

• Bit 3 – AREFD: AREF Digital Input Disable

When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre-

sponding PIN register bit will always read as zero when this bit is set. When an analog signal is

Table 14-2.

ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

Bit

76543210

0x09 (0x29)

HSEL

HLEV

ACM2

ACM1

ACM0

ACSRB

Read/Write

R/W

Initial Value

N/A

00000

Bit

7654

0x01 (0x21)

ADC6D

ADC5D

ADC4D

ADC3D

AREFD

ADC2D

ADC1D

ADC0D

DIDR0

Read/Write

R/W

Initial Value

0000

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