ATtiny261A datasheet(142/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

reference may be decoupled by an external capacitor at the AREF pin to improve noise

immunity.

The analog input channel and differential gain are selected by writing to the MUX5:0 bits in

ADMUX. Any of the 11 ADC input pins ADC10:0 can be selected as single ended inputs to the

ADC. The positive and negative inputs to the differential gain amplifier are described in Table

15-5.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input pair by the selected gain factor, 1x, 8x, 20x or 32x, according to the

setting of the MUX5:0 bits in ADMUX and the GSEL bit in ADCSRB. This amplified value then

becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is

bypassed altogether.

If the same ADC input pin is selected as both the positive and negative input to the differential

gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured

directly as the result of the conversion. This figure can be subtracted from subsequent conver-

sions with the same gain setting to reduce offset error to below 1 LSW.

The on-chip temperature sensor is selected by writing the code “111111” to the MUX5:0 bits in

ADMUX register when the ADC11 channel is used as an ADC input.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

15.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

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