ATtiny261A datasheet(145/292 Pages) ATMEL

145 / 292 page

145

8197A–AVR–10/09

ATtiny261A/461A/861A

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See Figure

15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,

the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger

source signal. Three additional CPU clock cycles are used for synchronization logic.

Figure 15-6. ADC Timing Diagram, Auto Triggered Conversion

In Free Running mode (see Figure 15-7), a new conversion will be started immediately after the

conversion completes, while ADSC remains high.

Figure 15-7. ADC Timing Diagram, Free Running Conversion

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

ATtiny261A Datasheet(PDF) 145 Page - ATMEL Corporation

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