ATtiny261A datasheet(148/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

Figure 15-8. Analog Input Circuitry

The capacitor in Figure 15-8 depicts the total capacitance, including the sample/hold capacitor

and any stray or parasitic capacitance inside the device. The value given is worst case.

The ADC is optimized for analog signals with an output impedance of approximately 10 k

Ω or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long the source needs to charge the S/H

capacitor, with can vary widely. The user is recommended to minmimize the charge transfer time

by using low impedant sources, only, with slowly varying signals.

Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid

distortion from unpredictable signal convolution. The user is advised to remove high frequency

components with a low-pass filter before applying the signals as inputs to the ADC.

15.9 Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. When conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run over the analog ground plane.

• Keep analog tracks well away from high-speed switching digital tracks.

• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.

• Place bypass capacitors as close to VCC and GND pins as possible.

Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as

described in Section 15.7 on page 147. This is especially the case when system clock frequency

is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as

described in Section 15.12 on page 152. A good system design with properly placed, external

bypass capacitors does reduce the need for using ADC Noise Reduction Mode

15.10 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2

n steps

(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

ADCn

IIH

1..100 k

CS/H= 14 pF

VCC/2

IIL

ATtiny261A Datasheet(PDF) 148 Page - ATMEL Corporation